The present invention is directed, in general, to a transistor device and, more specifically, to a transistor device having a dielectric region located under and in contact with a source region, a drain region and a channel region.
The advent of the integrated circuit has had a significant impact on various types of communication devices. The integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems. While operation speeds of these communication devices have dramatically increased, the demand for yet faster communication devices continues to rise. Thus, the semiconductor manufacturing industry continually strives to increase the overall speed of the integrated circuit. One way in which the semiconductor industry has increased the speed of the integrated circuit is to continue to shrink the size of the transistor. Over the last few years, the device size of the transistor has gone from 0.5 xcexcm to 0.32 xcexcm to 0.25 xcexcm and now transistor device sizes are heading to the 0.18 xcexcm range and below. As transistor device sizes have continued to dramatically decrease, with each decrease in size the semiconductor industry has faced new challenges.
One such challenge is that of eliminating parasitic capacitance as much as possible. As transistor geometries shrink, the time delay of signals propagating through the transistor are heavily influenced by the various parasitic capacitances inevitably associated with the structure, when fabricated according to the current state of the art. One of the principal remaining elements of transistor capacitance is the source-drain to substrate capacitance. This junction capacitance as a function of area is increasing as the technology advances. This is in part because one of the principal known failure mechanisms of a short channel transistor is controlled through the use of increased well doping. An increased well doping reduces the diode depletion layer thickness in the well which increases unit capacitance.
Another challenge is reducing xe2x80x9ccross-talk.xe2x80x9d As is well known, cross-talk results when electrical noise, created by transistor devices, travels through the capacitive coupling of the substrate and negatively affects the performance of opposing devices. Though cross-talk has been a well known phenomenon, up until recently it was of less concern. However, as a result of the use of multi-gigahertz operating frequencies in today""s RF devices, the significance of cross-talk has increased dramatically. In addition, with the increase in packing density and decrease in device size, transistor devices are being manufactured on the same chip and closer and closer together, which increases the relative importance of the cross-talk problem. Thus, as a result of the increased packing density and the decreased device sizes, both taken in conjunction with the cross-talk problems, device performance and integration issues are becoming increasingly apparent.
Silicon-on-insulator (SOI) already provides a solution to these problems. However, this approach can require the use of a very high current implanter and a very high thermal budget. The use of the very high current implanter and very high thermal budget generally leads to increased manufacturing time, complexity, and most importantly, increased manufacturing cost. Because of the three aforementioned drawbacks of SOI, the semiconductor manufacturing industry is generally unwilling to use the SOI structure on many conventional semiconductor devices.
Accordingly, what is needed in the art is a transistor device and a method of manufacture thereof, that does not experience the parasitic capacitance and xe2x80x9ccross-talkxe2x80x9d problems associated with the prior art transistors, and does not require the expense, time and effort to fabricate SOI substrates.
To address the above-discussed deficiencies of the prior art, the present invention provides a transistor device that avoids some of the problems associated with the prior art transistor devices. The transistor device includes a dielectric region located in a trench in a semiconductor substrate and a source region and a drain region located in the trench and at least partially on the dielectric region. The transistor device further includes a channel region located in the trench between the source region and drain region and at least partially on the dielectric region. In summary, the transistor device is isolated in a similar manner as those fabricated on a SOI substrate, however, without the use of SIMOX or wafer bonding.
The transistor device taught herein has reduced parasitic capacitance as compared to the prior art transistors. This is a result of the transistor device being isolated from the substrate and other possible capacitances by the dielectric region. The transistor device also benefits from being isolated from the substrate and other possible capacitances by stress relief oxides and nitride sidewall spacers, also included in the invention. Moreover, the dielectric region not only reduces parasitic capacitance, but it attempts to substantially reduce xe2x80x9ccross-talkxe2x80x9dcaused by transistors and other electrically noisy devices. Therefore, the dielectric region attempts to protect the transistor device from other electrically noisy transistors located on the semiconductor substrate, and vice versa.
In another aspect, the present invention teaches a method of manufacturing the transistor device. The method, in one advantageous embodiment, includes (1) forming a dielectric region in a trench in a semiconductor substrate, (2) forming a source region and a drain region in the trench and at least partially on the dielectric region, and (3) forming a channel region in the trench between the source region and drain region and at least partially on the dielectric region. Further included in the present invention is an integrated circuit, including the transistor device described above. The integrated circuit, may form part of an n-type metal oxide semiconductor (NMOS) device, a p-type metal oxide semiconductor (PMOS) device, a complementary metal oxide semiconductor (CMOS) device, or a BiCMOS device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.